--          knight rider
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity knightrider is
     port(clk : in std_logic;
          clr : in std_logic;
          q : out std_logic_vector(7 downto 0)
	  );

	attribute pin_assign : string;                 -- Pin assign
	attribute pin_assign of clk : signal is "5";
	attribute pin_assign of clr : signal is "39";
	attribute pin_assign of q   : signal is "43,44,1,2,3,4,8,9";
end knightrider;
-------------------------------------------------
architecture RTL of knightrider is
	signal work : std_logic_vector(3 downto 0);
	signal intclk : std_logic_vector(3 downto 0);

begin
    process(clk,clr) begin
    	  if clr='0' then
		intclk <= "0000";
          else
		if clk'event and clk = '1' then
			intclk <= intclk + '1';
		end if;
	  end if;
     end process;

     process(intclk(3),clr) begin
	if clr='0' then
		work <= "0000";
	else
		if intclk(3)'event and intclk(3) = '1' then
			work <= work + '1';
		end if;
	end if;
     end process;

     process(work) begin
	case work is
		when "0000" => q <="11111110";
		when "0001" => q <="11111101";
		when "0010" => q <="11111011";
		when "0011" => q <="11110111";
		when "0100" => q <="11101111";
		when "0101" => q <="11011111";
		when "0110" => q <="10111111";
		when "0111" => q <="01111111";
		when "1000" => q <="01111111";
		when "1001" => q <="10111111";
		when "1010" => q <="11011111";
		when "1011" => q <="11101111";
		when "1100" => q <="11110111";
		when "1101" => q <="11111011";
		when "1110" => q <="11111101";
		when "1111" => q <="11111110";
		when others => null;
	end case;
     end process;
end RTL;